Modern Very Large Scale Integration (VLSI) design flow typically has two major stages: the implementation stage and the sign-off stage. The implementation stage typically starts with a circuit design including a gate level netlist. Logic cells are placed on a layout and connected by metal lines. The logic cell placement and metal line routing are optimized based on timing analysis results. A Place-and-Route (P&R) tool is usually deployed at the implementation stage. The sign-off stage typically starts with final design out of P&R tool. Analysis is performed to simulate circuit behavior in real silicon. RC extraction tools and static timing analyzers (STAs) are typically used at the sign-off stage. A circuit design must be free of timing violations in its sign-off timing results before it can be delivered to a semiconductor foundry for manufacture.
Timing is analyzed in both the implementation stage and the sign-off stage. During a timing analysis, the design operates under a set of corner cases or modes (also referred to as scenarios), and timing results such as delay and slack of circuit paths are determined. During the implementation stage, to speed up the design cycle, designers tend to apply a limited set of scenarios compared with the sign-off stage. Even if the same scenario is analyzed in both stages, due to different implementations of how the circuit is modeled, there can be differences in timing analysis results.
In order to close the timing gap between the implementation stage and the sign-off stage, chip designers usually adopt an extra Engineering Change Order (ECO) flow, during which simple optimization moves (also referred to as adjustments or fixes) such as buffer resizing and insertion are applied to the whole logic design to fix timing violations identified by the sign-off timer. However, the typical ECO flow requires a long time to run and only permits simple optimization techniques. These issues arise because physical layout information such as the wire routing pattern is usually not available during the optimization process, yet the logical optimization moves can impact the wire routing pattern which in turn can impact the timing of the design, thus requiring multiple iterations during which full timing analysis is performed on the entire circuit.